Research Paper Analysis
VeriHGN: Heterogeneous Graph-Based Congestion Prediction for Chip Layout Verification
As Very Large Scale Integration (VLSI) designs continue to scale in size and complexity, layout verification has become a central challenge in modern Electronic Design Automation (EDA) workflows. In practice, congestion can only be accurately identified after detailed routing, making traditional verification both time-consuming and costly. Learning-based approaches have therefore been explored to enable early-stage congestion prediction and reduce routing iterations. However, although prior methods incorporate both netlist connectivity and layout features, they often model the two in a loosely coupled manner and primarily produce numerical congestion estimates. We propose VeriHGN, a verification framework built on an enhanced heterogeneous graph that unifies circuit components and spatial grids into a single relational representation, enabling more faithful modeling of the interaction between logical intent and physical realization. Experiments on industrial benchmarks, including ISPD2015, CircuitNet-N14, and CircuitNet-N28, demonstrate consistent improvements over state-of-the-art methods in prediction accuracy and correlation metrics.
Authors: Runbang Hu, Bo Fang, Bingzhe Li, Yuede Ji
Keywords: VLSI Physical Design, Chip Layout Verification, Congestion Prediction, Heterogeneous Graph Learning
Executive Impact & Key Findings
VeriHGN introduces a novel heterogeneous graph learning approach to address critical challenges in VLSI layout verification, offering substantial improvements in predictive accuracy and generalization.
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Peak Spearman Correlation (Cell-level)
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Cross-Design Generalization Improvement
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Lowest Cell-level MAE (ISPD2015)
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Relational Representation
Deep Analysis & Enterprise Applications
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Problem
Solution
Methodology
Performance
The Challenge of VLSI Congestion
Modern VLSI designs, with millions of cells and complex interconnects, face significant challenges in layout verification. Routing congestion, a critical bottleneck, can only be accurately identified after detailed routing, leading to prolonged turnaround times and increased costs. Traditional approaches struggle to integrate netlist connectivity and physical layout geometry effectively, often using loosely coupled models that fail to capture subtle correlations in dense and irregular regions.
Current methods primarily produce numerical congestion estimates without providing deeper insights into the multi-scale interactions that drive congestion, making hotspot identification and mitigation difficult.
VeriHGN: A Unified Heterogeneous Graph Approach
VeriHGN addresses these challenges by proposing a novel framework built on an enhanced heterogeneous graph that unifies circuit components (cells, nets) and spatial grids into a single relational representation. This allows for direct interaction between logical intent and physical realization, enabling more faithful modeling of complex routing demand.
Key aspects include a multi-resolution hierarchical grid and a message passing architecture that explicitly models interactions among different node types and across spatial scales. This unified formulation helps disentangle congestion sources, whether driven by local density, net-induced demand, or regional resource imbalance, leading to more accurate and actionable predictions.
Building the Heterogeneous Graph for Prediction
The core of VeriHGN lies in its sophisticated graph construction, integrating multiple views of a circuit into a single, comprehensive representation. This process exposes the primary sources of routing congestion—logical fanout, geometric proximity, and regional resource contention—as first-class entities in the graph structure.
The graph includes three node types: Cell nodes (standard cells, macros), Net nodes (electrical nets), and Grid nodes (spatial regions, organized hierarchically). Edges encode: Pin edges (cell-net incidences), Geometric cell edges (spatial proximity between cells), Grid adjacency edges (spatial neighborhoods), and Hierarchical grid edges (parent-child grid relationships).
This rich graph structure, combined with enriched feature engineering and relation-specific message passing, enables VeriHGN to jointly reason over logical connectivity and physical layout constraints for precise congestion prediction.
Superior Accuracy & Generalization
VeriHGN demonstrates consistent improvements over state-of-the-art methods across industrial benchmarks like ISPD2015, CircuitNet-N14, and CircuitNet-N28. It achieves superior performance in both error-based metrics (MAE, RMSE) and rank-based correlation metrics (Spearman, Kendall).
The model shows robust improvements in ranking-based metrics, crucial for hotspot identification, and consistently delivers uniform gains without trading off error minimization for ranking fidelity. Furthermore, VeriHGN exhibits improved cross-design generalization, retaining significantly higher Spearman correlation under zero-shot transfer compared to baselines, indicating its learned representations are more transferable across different process nodes.
Enterprise Process Flow: VeriHGN Graph Construction
Circuit design
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Hierarchical grid
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Netlist graph
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Cell-grid graph
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VeriHGN graph (unified)
0.692
Highest Spearman Correlation Achieved by VeriHGN (ISPD2015 Cell-level)
| Model | ISPD2015 (Cell-level) | CircuitNet-N14 (Cell-level) | CircuitNet-N28 (Cell-level) |
|---|---|---|---|
| GCN | 0.398 | 0.336 | 0.438 |
| GAT | 0.385 | 0.342 | 0.447 |
| CircuitGNN | 0.322 | 0.378 | 0.500 |
| MIHC | 0.689 | 0.512 | 0.522 |
| VeriHGN (Ours) | 0.692 | 0.513 | 0.548 |
Case Study: Cross-Design Generalization
VeriHGN demonstrates superior transferability across different process nodes. For instance, when trained on CircuitNet-N28 and tested on CircuitNet-N14, VeriHGN retained 43.7% of its in-domain Spearman correlation, significantly outperforming MIHC's 32.8% retention. This highlights VeriHGN's ability to learn more robust and design-agnostic representations of routing demand, making it a more practical solution for diverse industrial applications.
The unified heterogeneous graph and enriched feature engineering contribute to this enhanced generalization, reducing reliance on training data from every new process node.
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Annual Cost Savings
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Annual Engineering Hours Reclaimed
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Your Implementation Roadmap
A phased approach to integrate advanced congestion prediction into your EDA workflow for maximum impact.
Phase 01: Initial Assessment & Data Preparation
Evaluate current EDA workflow, gather placement and routing data, and establish a baseline for congestion. Prepare historical design data for model training and validation.
Phase 02: Model Adaptation & Training
Adapt the VeriHGN framework to your specific technology nodes and design library. Train the heterogeneous graph model using your prepared datasets, focusing on critical performance metrics.
Phase 03: Integration & Validation
Integrate the trained VeriHGN model into your pre-routing stage. Validate its predictions against detailed routing results on new designs, refining the model for optimal accuracy and actionable insights.
Phase 04: Continuous Optimization & Scalability
Deploy the solution at scale across your design teams. Establish a feedback loop for continuous model improvement and explore extensions for timing-aware prediction and further automation.
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